Fangxin (Leon) Liu is an Assistant Professor and Ph.D. Supervisor in the School of Computer Science at Shanghai Jiao Tong University (SJTU). He is a core member of the Scalable Computing and Systems Lab, collaborating closely with Prof. Haibing Guan and Prof. Li Jiang. He also serves as a Research Fellow at the Shanghai Qi Zhi Institute.
His research focuses on computer architecture and hardware-software co-design for efficient AI systems, particularly for LLM/VLM, Computing-in-Memory (CIM/PIM) architectures, and Brain-inspired Computing.
Dr. Liu has published over 60 papers, including 40+ in CCF Tier-A venues (e.g., ISCA, MICRO, ASPLOS, HPCA, PPoPP). His work has been recognized with the Best Paper Finalist at ISCA 2026, the Outstanding Paper Award at ACM MM 2025 (Systems Theme), the Best Paper Award at DATE 2022, and the HUAWEI Spark Award (火花奖).
40+CCF Tier A1st / Corr. Author
60+Total Pubs1st / Corr. Author
40%Cost SavedApplied at Huawei, Ant, etc.
6+Major AwardsBest Paper / Dissert.
His architectural and system solutions have been deployed by leading technology companies, including Huawei, Ant Group, ZTE, and Yizhu Tech., resulting in up to 40% computational cost reductions in large-scale AI deployments.
🔥 Recruitment
Our team is actively seeking self-motivated PhD, Master, and Undergraduate students interested in Computer Architecture, Efficient AI acceleration, and PIM Design. If you are interested, please email me your CV.
News
Apr. 27, 2026
🏆 Best Paper Candidate: Our paper "COMET: A Cooperative Scheduling Framework for Concurrent PIM/CPU Execution on Mobile Devices" has been selected as one of the five finalists for the Best Paper Award at ISCA 2026. Congratulations to Yilong and all co-authors on this prestigious honor!
Apr. 14, 2026
🛠️ Our high-performance Attention Sparse Acceleration Kernels have been officially integrated into the Huawei CANN (Compute Architecture for Neural Networks) software stack. Furthermore, our team has successfully passed the CANN Core Developer Certification, marking a significant step in bridging architectural research with large-scale industrial infrastructure.
Apr. 06, 2026
🚀 ACL 2026: Our paper (CSD) on Speculative Decoding Acceleration has been accepted to the ACL 2026 Main Conference. Congratulations to Xuwen and all co-authors!
Mar. 28, 2026
🚀 ISCA 2026: Three papers covering Sparse Matrix Multiplication (Harmonia), MoE Inference Optimization (STEP), and Mobile PIM/CPU Scheduling (COMET) have been accepted to the 53rd International Symposium on Computer Architecture. Congratulations to Jingkui, Ning, Yilong, and all co-authors!
Feb. 24, 2026
🚀 Five papers covering Neuromorphic Computing, 3DGS, MoE and PCIe Simulation have been accepted to DAC 2026. Congratulations to Haomin, Chenyang, Zhibai and all co-authors!
Feb. 04, 2026
📄 Our joint technical report with Huawei MindSpore team, HyperOffload, is released. It cuts peak memory by 26% with end-to-end performance lossless. arXiv: 2602.00748
Jan. 24, 2026
📄 Our paper "NICE: Deep Neural Network Acceleration via Hardware-Friendly Index Assisted Compression" has been accepted to ACM TACO 2026.
Jan. 21, 2026
🏆 Our work “TFLOP” has received the Special Feature Award at the ASP-DAC University LSI Design Contest 2026.
Nov. 26, 2025
📄 Our two papers on MoE memory bottleneck and 3DGS rendering have been accepted to ASPLOS 2026.
Nov. 11, 2025
📄 Two papers on graph-based memory and sparse Transformer acceleration accepted to PPoPP 2026.
Nov. 11, 2025
📄 Three papers on Modular Multiplication, LLM, and CPU-GPU computing accepted to DATE 2026.
